Representative embodiments relate to a semiconductor device, and more particularly, to a cell structure of a semiconductor device.
In general, smaller semiconductor devices are being fabricated in accordance with decreasing design rules and increased integration density. A semiconductor device may include an active region, gate patterns, bit line pattern, storage nodes, and the like. The active region may be arranged in a semiconductor substrate in a direction diagonal to the gate patterns or the bit line pattern in order to increase integration density per unit area and decrease size. However, a diagonal arrangement does not take into consideration the alignment system of a semiconductor photolithography apparatus, which moves horizontally and vertically in rows and columns. In other words, it is difficult to accurately align the gate patterns, the bit line pattern and the storage nodes with the active region. Accordingly, the gate patterns, the bit line pattern, and the storage nodes may not have good electrical characteristics with the active region, and thus deteriorating the semiconductor device.
Illustrative embodiments provide a cell structure of a semiconductor device, which optimizes the arrangement of an active region, a gate pattern and a bit line pattern, for example, increasing the exposed area of the active region between the gate pattern and the bit line pattern.
According to illustrative embodiments, a cell structure of a semiconductor device includes an active region and an inactive region in a semiconductor substrate. The active region has a concave portion, and the inactive region defines the active region. A gate pattern is disposed in the first active region and the inactive region. The gate pattern in the first active region is arranged perpendicular to the first active region. A landing pad on the first active region and the inactive region contacts the active region. A bit line pattern on the inactive region intersects the gate pattern perpendicularly, the bit line pattern being electrically connected to the landing pad and having a first protrusion corresponding to the concave portion of the active region.
The concave portion of the first active region may be in a selected lateral portion of the first active region, which overlaps a portion of the first gate pattern. The first gate pattern may extend across the concave portion of the first active region, and below the first protrusion of the bit line pattern. The first gate pattern may also extend from upper portions of the first active region and the inactive region toward lower portions of the first active region and the inactive region.
The cell structure may further include a bit line contact between the first landing pad and the bit line pattern. The bit line contact contacts the first landing pad and the bit line pattern on the inactive region.
The first protrusion of the bit line pattern may extend from a first lateral portion of the bit line pattern and overlap the concave portion of the first active region.
The cell structure may further include a second active region having the same shape as the first active region, and a second gate pattern in the second active region having the same shape as the first gate pattern. The bit line pattern may have a second protrusion extending from a second lateral portion of the bit line pattern and having the same shape as the first protrusion. The second active region may be arranged horizontally with respect to the first active region along a row of the semiconductor substrate.
The first and second gate patterns may be parallel to each other and extend across the concave portion of the first active region, a concave portion of the second active region, and the first and second protrusions of the bit line pattern.
The second protrusion of the bit line pattern may overlap a lateral portion of the second active region, which is located opposite to the concave portion of the second active region.
The bit line pattern may have third protrusions, having the same shape as the first and second protrusions, positioned repeatedly along the first and second lateral portions of the bit line pattern. Also, the cell structure may further include third active regions corresponding to the third protrusions and arranged along the bit line pattern in the semiconductor substrate, the third active regions having the same shape as the first active region and being positioned vertically and horizontally with respect to the first and second active regions. The cell structure may further include third gate patterns in the third active regions, the third gate patterns having the same shape as the first and second gate patterns, and second landing pads located between the third gate patterns and contacting the third active regions to electrically connect the third active regions to the bit line pattern.
According to other illustrative embodiments, a cell structure of a semiconductor device includes a first active region in a semiconductor substrate, the first active region having first and second lateral portions, and an inactive region in the semiconductor substrate, defining the first active region. First and second gate patterns intersect the first lateral portion of the first active region parallel to one another, separated by a first width in the first active region, and intersect the second lateral portion of the first active region diagonally extending away from one another other over a predetermined distance, and becoming parallel to one another, separated by a second width greater than the first width in the inactive region. A first landing pad is on the first active region and the inactive region is in contact with the first active region, the first landing pad being positioned between the first and second gate patterns. A bit line pattern is on the inactive region and intersects the first and second gate patterns, the bit line pattern having a first protrusion. The bit line pattern is electrically connected to the first landing pad through the first protrusion.
The first active region may overlap the first protrusion of the bit line pattern. The first and second gate patterns may extend below the first protrusion of the bit line pattern. Also, the first and second gate patterns may extend from upper portions of the first active region and the inactive region toward lower portions of first active region and the inactive region.
The cell structure may further include a bit line contact between the first landing pad and the bit line pattern. The bit line contact contacts the first landing pad and the first protrusion.
The first protrusion of the bit line pattern may extend from a first lateral portion of the bit line pattern toward the first active region and contact the bit line contact.
The cell structure may further include second and third active regions having the same shape as the first active region, and positioned diagonally with respect to the first active region in rows of the semiconductor substrate. The first and second gate patterns may be respectively located in the second and third active regions separated by the second width.
The bit line pattern may have second protrusions, having the same shape as the first protrusion, positioned repeatedly along the first lateral portion of the bit line pattern. Also, the cell structure may her include third gate patterns and fourth active regions located along the bit line pattern in the semiconductor substrate to correspond to the second protrusions; and fourth active regions corresponding to the second protrusions and arranged along the bit line pattern in the semiconductor substrate. The fourth active regions may have the same shape as the first through third active regions. The third gate patterns have the same shape as the first and second gate patterns, and the cell structure may further includes second landing pads located between the third gate patterns and contacting the fourth active regions to electrically connect the fourth active regions to the bit line pattern at the second protrusions.
According to still other illustrative embodiments, a cell structure of a semiconductor device includes an active region in a semiconductor substrate and an inactive region defining the active region, the active region having a first lateral portion and a second lateral portion. A first gate pattern intersects the first lateral portion of the active region and is disposed in the active region. A second gate pattern intersects the first lateral portion parallel to the first gate pattern, and intersects the second lateral portion either parallel to the first gate pattern or diagonal to the first gate pattern and then parallel to the first gate pattern in a vicinity of the inactive region. A landing pad is positioned on the active and inactive regions between the first and second gate patterns, the landing pad contacting the active region. A bit line pattern intersects the second gate pattern and electrically connects to the landing pad, the bit line pattern having a protrusion overlapping the active region.
The cell structure may further include a bit line contact between the landing pad and the bit line pattern. The bit line contact is on the inactive region or on the active and inactive regions, and contacts the landing pad and the bit line pattern.